Technical disclaimer

CAN Topology Lab is a fast pre-layout and what-if tool. It does not replace SPICE simulation, prototype measurements or compliance testing (ISO 11898-2, SAE J2284, CiA 601 and the vehicle or machine maker's requirements).

Main model limitations

• Differential mode only, with a fixed common mode: no EMC emissions/immunity, CANH/CANL asymmetries or ground shift.
• Uniform impedance per segment and no crosstalk between cables.
• Closed-form formulas for PCB traces (typical accuracy ±5–10%); use a field solver for sign-off values.
• Connectors as equivalent line segments; lumped blackbox cells.
• Power based on datasheet supply currents (maximum values).
• One transmitter at a time: arbitration with two TXs is not simulated.
• Bit check at the nominal sample point (shifted by the propagation delay): oscillator tolerance, transceiver timing asymmetry, MCU–transceiver delays, CAN bit-timing segments and transmitter delay compensation (TDC) are not modelled. Keep a time margin around the sample point.
• The waveform is the differential voltage CANH − CANL; the receiver output (RXD) is not modelled.

Always check the parameters against the datasheets of the components you use.