CAN Topology Lab — Wiki
Interactive CAN / CAN-FD bus simulator: topology, transmission lines, PCBs, connectors, filters, transceivers (IBIS models too), reflections, sampling check and power. File:
canfd_topology_lab.html(a single file, works offline in any modern browser). This wiki is built into the page: reopen it with the 📖 Wiki button at the top or with theF1key.
1. What it is for and who it is for
A CAN bus is a twisted pair of wires (CANH and CANL) with several nodes connected to it. At low speed (125–500 kbit/s) "the wires just have to get there": the signal is slow compared with the time it takes to travel along the cable. With CAN-FD (2, 5, 8 Mbit/s in the data phase) bits last 125–500 ns and edges a few tens of ns: the cable behaves as a transmission line, and every discontinuity (open ends, stubs, connectors, PCB traces, capacitors) produces reflections that can make a node read a wrong bit.
The simulator lets you:
- draw the real topology (backbone, stubs, stubs derived from stubs, PCB boards, connectors, cables);
- see the waveform at any point and the animation of waves travelling and bouncing;
- know immediately whether every receiver samples every bit correctly, with the margin in volts;
- evaluate terminations, PCB stack-ups, cable losses, pin capacitances, filters and ESD protections;
- use the transceiver's IBIS model (non-linear simulation);
- estimate the power drawn and dissipated by every node and every termination.
For the electronics engineer: a fast pre-layout / what-if tool, before moving to SPICE or to the lab. Every parameter comes from a datasheet (cables, laminates, connectors, transceivers, diodes). For the less experienced: a visual way to understand why the CAN rules exist (two terminations, short stubs, no stars) by playing with the diagram.
2. Quick start in 5 minutes
- Open the file
canfd_topology_lab.htmlwith a double click (Chrome, Edge, Firefox). Nothing to install. - Look at the "Diagnostics" panel: green with ✓ means every node reads the bits correctly. Red means at least one node gets them wrong.
- Try a preset at the top (orange/grey buttons):
- Recommended → correct bus, all green.
- No terminations → look at the waveform: huge ringing and misread bits.
- Too many terminations → the signal drops (DC load too low).
- Long stubs → ringing after every edge.
- Click the small green resistors at the ends of the backbone: you remove/insert them. The simulation updates by itself.
- Move the probe (the yellow "PROBE" dot): drag it along a cable, or click the empty yellow dots at the ends. The plot shows the voltage at that point.
- Press ▶ Play under the plot: the cables are coloured (orange = positive voltage, blue = negative) and you see the waves travel and bounce.
- Hover the ? icons: they explain the less intuitive parameters.
💡 Made a mistake? Ctrl+Z undoes, Ctrl+Y redoes. The configuration is remembered by the browser; Save downloads it as a file. The EN | IT switch in the top bar changes the language.
3. Minimal glossary
| Term | Meaning |
|---|---|
| CANH / CANL | The two bus wires. You always look at their difference Vdiff = CANH − CANL. |
| Dominant (bit 0) | A node "drives" the bus: Vdiff ≈ 2 V. It always wins over recessive. |
| Recessive (bit 1) | Nobody drives: Vdiff ≈ 0 V, the bus is held at rest by the terminations. |
| Receiver thresholds | Vdiff > 0.9 V → dominant; Vdiff < 0.5 V → recessive; in between = undefined (red band in the plot). |
| Sample point | Instant, in % of the bit, at which the controller reads the bit (typically 70–80% in FD). |
| Backbone | The main bus line, terminated at both ends. |
| Stub | A branch from the backbone to a node. Keep it short. |
| Termination | 120 Ω resistor between CANH and CANL at both ends of the backbone; together they make 60 Ω. |
| Z0 / Zdiff | Differential characteristic impedance of the pair (CAN cable: 120 Ω). |
| Reflection, Γ | When the wave meets an impedance different from Z0, part of it comes back. Γ = 0 no reflection, +1 everything reflected (open circuit), −1 reflected inverted (short). |
| NVP | Propagation velocity relative to light (0.66–0.76 for CAN cables → 4.4–5 ns/m). |
| PCB stack-up | The sequence of copper and dielectric layers of a printed circuit board. |
| Microstrip / stripline | Trace on an outer layer with a plane below / inner trace between two planes. |
| IBIS | Standard vendor format describing the electrical behaviour of a chip's pins (voltage-current curves, edges). |
| CMC | Common-mode choke: EMI filter in series with the lines. |
| TVS / ESD | Overvoltage protection diodes. They add capacitance to the bus. |
4. The interface, piece by piece
4.1 Top bar
- Presets: ready-made example topologies. When you change something it becomes "Custom".
- Status (green/red pill): number of samples, time step, computation time, or the error message.
- EN | IT: interface language (the setting is remembered; an untouched preset is rebuilt in the new language, an edited topology keeps its names).
- 📖 Wiki (or
F1): this guide. - 📚 Libraries: PCB boards/stack-ups, cables, connectors, blackboxes, transceivers/IBIS.
- ↶ ↷: undo / redo.
- Save / Load: complete configuration (topology + libraries) as JSON. Also loads files from the first version.
- CSV: exports the waveform at the probe (time, Vdiff, CANH, CANL, TX command).
4.2 Topology (the diagram)
| Element | Look | Actions |
|---|---|---|
| Backbone and stubs | red/blue pair (cable) or orange/copper (PCB trace) | click → menu: probe here, new stub/sub-stub, connector, blackbox, split segment, intermediate termination, properties |
| Tap point | white circle on the parent branch | drag to move it |
| Node (transceiver) | box with name and TX/RX badge | drag to lengthen the stub's last segment; click → properties; click on RX → it becomes the transmitter |
| Value chips | dark labels (⟷ 8.00 m, 120 Ω, TCAN4551-Q1…) |
click → small in-place editor |
| Resistors | green badges (inserted) / grey crossed out (removed) | click → insert/remove |
| Connector | small grey rectangle (pink = choke) | click → type, equivalent |
| Blackbox | teal ≈ square (filter) or yellow ⚡ (ESD) |
click → type, summary |
| Board | coloured dashed box with a label | click the label → stack-up; drag the label along the edge |
| Probe | pulsing yellow dot | drag along the branch; empty dots = quick spots |
| Γ and P | small texts near the ends | reflection coefficient and power in the termination |
| ▲ row in the nodes | ▲ 530 mW diss · 48 mA |
estimated dissipated power and supply current; click → plot |
Zoom and navigation: Ctrl + wheel (or trackpad pinch), − / % / + buttons, +, −, 0 keys. Drag the background to pan. The 🖱 button enables zoom with the wheel alone.
Shortcuts: Shift while dragging = fine 1 mm step · Space play/pause · Del deletes the selected element · Esc closes menus and windows · F1 wiki.
Not to scale: every segment is drawn with a logarithmic length (a 2 cm PCB trace and an 8 m cable both stay readable). Real values are always in the chips.
4.3 Right panel (Inspector)
Shows all the properties of the selected element: - Bus & signal (nothing selected): bit rate, bit sequence, high-impedance driver, Vcm, simulation window, time step, sample point, access to the libraries. - Backbone: segment chain, end and intermediate terminations. - Node/stub: name, position, drawing side, stub chain (segments, connectors, blackboxes reorderable with ↑ ↓), transceiver, Cesd, VSUP, VCCOUT load, termination, power, Γ, margin, actions (sub-stub, probe, duplicate, delete). - Probe: branch and exact position.
4.4 Waveform
- Views: Vdiff, CAN_H / CAN_L, Power.
- Labels at the top: bit value (
0 · D,1 · R,idle). - Green/red dots: value at the sample point, OK or error.
- Red band: undefined region 0.5–0.9 V.
- Grey dashed line: unloaded TX command (reference).
- 📌 Pin trace: stores the current curve to compare it after a change (up to 4).
- Zoom: wheel on the plot, drag to scroll, double click = all; "Edge zoom" goes to the first edge.
- Click on the plot: moves the animation time cursor.
4.5 Diagnostics
- Verdict: all receivers OK, or how many fail.
- Bus DC load: must be between 50 and 65 Ω.
- Active terminations: normally 2.
- Minimum margin and settling at the probe (see §7.12).
- Peak / minimum, total node capacitance.
- Receiver table: distance and delay from the TX, margin, settling, result. Click a row → probe on that node.
- Warnings: unterminated ends, load out of range, long stubs, PCB pairs far from 120 Ω, very short connectors.
4.6 Consumed and dissipated power
- % dominant bus: fraction of time dominant in real traffic (50% typical, 100% worst case).
- Nodes table: VSUP, ISUP, power drawn, delivered to the bus, dissipated in the chip (estimate, dominant/recessive, peak).
- Terminations table: power in dominant, recessive, estimate, peak.
- Totals. Click a row → power-versus-time plot.
5. The libraries
Open them from 📚 Libraries or from the buttons in the segment menus. Every change applies to the simulation immediately.
5.1 PCB boards and stack-ups
- Board list (each board = one physical PCB, with a colour and a box on the diagram). "Duplicate" for two identical PCBs.
- Stack-up from the top: copper (thickness, "reference plane" flag), dielectric (thickness, εr, tan δ), solder mask. Preset 2-, 4- and 6-layer stack-ups.
- Differential pairs: layer, width W, spacing S, optional fixed Zdiff from a field solver.
- Real-time cross-section: layers, traces, highlighted reference plane, W/S/h dimensions, indicative field lines.
- Results: structure (microstrip/stripline/embedded), Zdiff, single-ended Z0, εeff, velocity and delay (ps/mm), distance from the plane, losses at 10 and 100 MHz.
5.2 Cables
Z0, NVP, DC resistance per conductor (Ω/km), datasheet attenuation table (MHz, dB/100 m) and plot of the curve used by the simulator.
5.3 Connectors and chokes
Two formats: L·C·R (series inductance, capacitance between contacts, contact resistance) or Z·delay (high-speed connectors). Shows the equivalent Z, τ, L and C.
5.4 Blackbox (filters, ESD)
Two-port cell inserted in series in the chain. Side A = towards the bus, side B = towards the node.
| Group | Parameter | Where to get it |
|---|---|---|
| Series branch (differential) | Series R [Ω] | series resistors (sum of both lines), choke DCR |
| Series L [nH] | differential leakage inductance of the CMC, ferrites | |
| C across the branch [pF] | parasitic capacitance → self-resonance (SRF) | |
| Shunts A and B | C per line to GND [pF] | EMI capacitors, C_j of ESD diodes |
| C between CANH and CANL [pF] | differential capacitor, line-to-line C | |
| R between the lines [Ω] | integrated termination / split termination (2×60 Ω = 120 Ω) | |
| Clamp: trigger V [V], dynamic R [Ω], bi/unidirectional | V_BR / V_clamp and R_DYN from the TVS datasheet |
The window shows the schematic, the |S21| response between 120 Ω ports with the CAN band highlighted, the −3 dB frequency, the self-resonance and a warning if the cell cuts into the useful band.
5.5 Transceivers and IBIS
- Linear model: RID, CI, CID, open-circuit voltage and dominant Rout, 10–90% rise time, recessive/dominant ISUP.
- ⬆ Import IBIS…: load an
.ibs, choose the models for CANH and CANL, the corner (typ/min/max), whether to include the package C and whether to remove the internal delay. Preview of VOD, RID, edges and warnings. Option "assign to all nodes". - For an IBIS transceiver: "Use the non-linear IBIS model" switch, plots of the V-I curves, of the differential driver against the 60 Ω load, of the switching coefficients and of the edges.
The TCAN4551-Q1 has no official IBIS model: TI suggests using the TCAN1044A-Q1 one (same bus design). Supply currents remain those of the TCAN455x datasheet.
6. Recipes
6.1 Checking an existing topology
- Start from Recommended and adapt the backbone chain (Backbone panel): one segment per cable or trace, a connector where there are connectors.
- Add stubs with click on the cable → New stub here, then enter length and medium of every segment.
- Choose the TX (TX/RX badge) and set the real data-phase bit rate and sample point.
- Check Diagnostics. Repeat making the farthest nodes the TX, one at a time: the worst case changes with the transmitter.
6.2 How long can a stub be?
- Select the stub and drag the node to lengthen it (Shift for 1 mm steps).
- Watch margin and settling: when settling approaches the sample point you are at the limit.
- Use 📌 Pin trace to compare two lengths.
6.3 Choosing the terminations
- Two 120 Ω at the ends of the backbone → DC load ≈ 60 Ω, Γ ≈ 0 at the ends.
- Try Single termination and Too many terminations to see the effects.
- Intermediate terminations (on the backbone, with the line continuing) only for experiments.
6.4 Modelling nodes on the same board
- Boards library → new board with your PCB stack-up and the CAN pair (W, S, layer).
- In the chain use the medium "Board X · pair" for the PCB segments.
- Nodes at the end of PCB segments are grouped in the board's box.
6.5 Inserting an ESD protection or a filter
- Blackbox library → duplicate an example and enter your part's values.
- On the diagram: click the stub segment near the connector → Insert blackbox here (or "+ Blackbox" in the chain).
- Check in the library that the −3 dB frequency is well above the CAN band.
6.6 Using an IBIS model
- Libraries → Transceivers and IBIS → Import IBIS… →
.ibsfile. - Check that VOD @60 Ω is between 1.5 and 3 V and read the warnings.
- Tick "assign to all nodes" or choose the model node by node.
- Repeat with the min and max corners for the corner cases.
6.7 Estimating power and temperature
- Set each node's VSUP and any load on VCCOUT.
- Set the % dominant in the Power panel (100% = bus stuck dominant, worst case).
- Estimated junction temperature: Tj ≈ Ta + RθJA · P_diss (RθJA from the package datasheet).
7. The math behind the simulator
7.1 Transmission line
A pair of conductors with inductance L' and capacitance C' per metre (losses neglected):
Z0 = √(L'/C') characteristic impedance [Ω]
v = 1/√(L'·C') = c/√εeff = NVP·c propagation velocity [m/s]
t_pd = ℓ / v delay of a segment of length ℓ
Example: NVP = 0.76 → v ≈ 2.28·10⁸ m/s → 4.4 ns/m.
When is the line model needed? When the round-trip delay is comparable with the rise time: 2·t_pd ≳ t_r/3 (rule of thumb).
7.2 Reflections
An incident wave V⁺ on a load Z_L:
Γ = (Z_L − Z0) / (Z_L + Z0) V_reflected = Γ·V⁺
T = 1 + Γ V_transmitted = T·V⁺
| Load | Γ |
|---|---|
| Z_L = Z0 (terminated) | 0 |
| open (∞) | +1 |
| short (0) | −1 |
| 120 Ω ∥ RID (60 kΩ) on Z0 = 120 Ω | ≈ −0.001 |
| receiver without termination (RID ≫ Z0) | ≈ +1 |
Stub junction on the backbone (three branches of Z0): the arriving wave sees two Z0 in parallel, i.e. Z0/2:
Γ = (Z0/2 − Z0)/(Z0/2 + Z0) = −1/3 → 2/3 of the amplitude continues in each branch
The stub end is almost open (Γ ≈ +1): the wave returns to the junction after 2·t_pd_stub and a train of reflections is born, the ringing.
7.3 Traveling-wave model (digital waveguide)
On each segment the voltage is the sum of a forward wave (a) and a backward wave (b):
V(x,t) = a(t − x/v) + b(t + x/v)
I(x,t) = [a(t − x/v) − b(t + x/v)] / Z0
Waves travel without distortion for the delay t_pd (plus losses, §7.6). All the computation happens at the nodes (junctions). At a node with incident waves a_i on lines of impedance Z_i, shunt conductances G and a Norton source I_s:
2·Σ (a_i / Z_i) + I_s + I_C
V = ─────────────────────────────── (KCL + voltage continuity)
Σ (1/Z_i) + Σ G + G_s + G_C
b_i = V − a_i outgoing wave on each line
Nodes are independent at every step, because the lines "delay" the information. Each segment's delay is interpolated (fractional delay):
a(n − D) ≈ (1 − f)·h[i₀] + f·h[i₀+1], D = t_pd/Δt, i₀ = ⌊n − D⌋, f = (n − D) − i₀
Time step: Δt = min(Δt_max, t_pd,min / 4), i.e. at least 4 samples for the shortest segment. Points closer than 4 mm are merged.
7.4 The transmitter (linear model)
Differential Thevenin source (V_open, R_dom) in dominant. With "high-impedance driver in recessive", the conductance varies with the state s(t) ∈ [0,1]:
G_s(t) = s/R_dom + (1 − s)/RID I_s(t) = s·V_open / R_dom
VOD (into R_L) = V_open · R_L / (R_L + R_dom)
The edge is a smoothstep s = u²(3 − 2u) of total duration t_tot. The 10–90% time is t_10-90 ≈ 0.608·t_tot.
7.5 Node capacitances (pins, ESD, cells)
Differential capacitance at a transceiver node:
C_diff = CID + CI/2 + Cesd/2 (two capacitances to ground in series = half)
Trapezoidal integration ("companion model"):
G_C = 2C/Δt
i_C(n) = G_C·V(n) − I_h(n) I_h(n+1) = G_C·V(n) + i_C(n)
7.6 Frequency-dependent losses
Cable: start from the datasheet points A_k [dB/100 m] at f_k. Log-log interpolation between points; below the first point it joins the DC loss; above the last, a slope between √f and f. The DC loss comes from the conductor resistance:
α_DC = R_loop / (2·Z0) [Np/m], R_loop = 2·R_conductor, 1 Np = 8.686 dB
PCB trace (skin effect + dielectric):
R_s(f) = √(π·f·μ0·ρ_Cu) surface resistance (ρ_Cu = 1.72·10⁻⁸ Ω·m)
R(f) ≈ √(R_DC² + (k·R_s/W)²) per conductor; k = 1 microstrip, ½ stripline
α_c = R(f) / Z_diff [Np/m] (= 2R / (2·Z_diff))
α_d = π·f·√εeff·tanδ / c [Np/m]
A(f) = 8.686·(α_c + α_d) [dB/m]
In the time domain: for every segment the attenuation above DC, T(f) = ℓ·[A(f) − A(0)], is approximated by a cascade of first-order shelf filters, each with a step d_k [dB] around f_k:
H_k(s) = (ω_p/ω_z)·(s + ω_z)/(s + ω_p), ω_z/ω_p = 10^(d_k/20)
The steps are found with non-negative least squares plus iterative refinement, up to ~30 dB of attenuation. Discretization is bilinear with prewarping (K = 2/Δt):
b0 = g(K + ω_z)/(K + ω_p), b1 = g(ω_z − K)/(K + ω_p), a1 = (ω_p − K)/(K + ω_p), g = ω_p/ω_z
y[n] = b0·x[n] + b1·x[n−1] − a1·y[n−1]
7.7 PCB trace impedance
Microstrip (Hammerstad–Jensen), u = W/h:
Z0,air(u) = 60·ln( F(u)/u + √(1 + 4/u²) ), F(u) = 6 + (2π − 6)·exp(−(30.666/u)^0.7528)
εeff(u) = (εr+1)/2 + (εr−1)/2·(1 + 10/u)^(−a·b)
Z0 = Z0,air / √εeff (with a correction for the copper thickness t)
Inner microstrip (embedded): εeff ≈ εr·(1 − e^(−1.55·h_above/h)). Stripline (IPC-2141), with b = distance between the planes:
Z0 = (60/√εr)·ln( 1.9·b / (0.8·W + t) )
asymmetric: Z0 ≈ 2·Za·Zb/(Za + Zb), Za,b = Z0(b = 2·h₁,₂ + t)
Coupled differential pair (IPC approximations):
microstrip: Z_diff ≈ 2·Z0·(1 − 0.48·e^(−0.96·S/h))
stripline: Z_diff ≈ 2·Z0·(1 − 0.347·e^(−2.9·S/b))
Typical accuracy ±5–10%. For sign-off values use a field solver and enter a "Fixed Zdiff".
7.8 Connectors
The connector is a short equivalent line segment:
L·C·R format: Z = √(L/C), τ = √(L·C)
Z·τ format: given directly
contact R: attenuation exp(−R/(2Z))
Minimum delay 20 ps: below this value the effect is negligible and the time step would become too small.
7.9 Blackbox cells
Series branch R + L (with C_p in parallel) between nodes A and B, trapezoidal integration:
G_s = 1/(R + 2L/Δt)
i(n) = G_s·v(n) + h(n) v = V_A − V_B
h(n+1) = G_s·[ v(n) − (R − 2L/Δt)·i(n) ]
C_p: i_p = G_p·v − I_hp, G_p = 2C_p/Δt
The two nodes are solved together (2×2 system, Newton when there are clamps):
(d_A + G_b)·V_A − G_b·V_B = n_A − h_b
−G_b·V_A + (d_B + G_b)·V_B = n_B + h_b G_b = G_s + G_p, h_b = h − I_hp
Shunt on each side:
C_diff = C_line_GND/2 + C_line_line G = 1/R_line_line
Clamp (per line, with V_H = Vcm + V/2 and V_L = Vcm − V/2):
i(v) = (v − Vc)/R_dyn if v > Vc; (v + Vc)/R_dyn if v < −Vc (bidirectional; −0.7 V if unidirectional)
I_diff = ½·[ i(V_H) − i(V_L) ]
|S21| response (small signal, 120 Ω ports), with the ABCD matrix of the shunt–series–shunt cell:
[A B; C D] = [1 0; Y_A 1]·[1 Z_s; 0 1]·[1 0; Y_B 1]
S21 = 2 / (A + B/Z0 + C·Z0 + D)
SRF = 1 / (2π·√(L·C_p))
7.10 IBIS transceiver (non-linear)
IBIS conventions: positive current flows into the pin. [Pullup] and [POWER Clamp] tables as a function of V_ref − V_pin; [Pulldown] and [GND Clamp] as a function of V_pin. - CANH uses the pull-up (open-source driver towards VCC). - CANL uses the pull-down (open-drain driver towards ground).
Switching coefficients K(t), from the fixture waveforms (R_fix towards V_fix):
I_fix = (V_fix − V(t))/R_fix − C_fix·dV/dt
K(t) = [ I_fix − I_clamp(V) − C_comp·dV/dt ] / I_table(V)
K is normalized to 1 at steady state (DC tables) and the driver's internal delay is removed.
Differential equivalent (fixed Vcm, V = Vdiff):
I_drive(V,t) = ½·[ K_H(t)·(−I_pullup(VCC − Vcm − V/2)) + K_L(t)·I_pulldown(Vcm − V/2) ]
I_clamp(V) = ½·[ I_cl,H(Vcm + V/2) − I_cl,L(Vcm − V/2) ]
C_diff = (C_comp,H + C_comp,L)/4 + C_pkg/2
Node solution (Newton, a few iterations per step):
F(V) = D·V − N + g(V) = 0, g(V) = −I_drive(V,t) + I_clamp(V)
V ← V − F(V)/F'(V)
Equivalent quantities shown in the library: - VOD into R_L: zero of I_drive − I_clamp − V/R_L; - Thevenin equivalent from the solutions at 45 and 65 Ω; - RID = 1/(dI_clamp/dV) at 0.
7.11 Bus DC load
1/R_DC = Σ 1/R_terminations + Σ 1/RID_receivers ISO 11898-2 target: 50–65 Ω
7.12 Bit check
For each bit i, at the node with delay t_d from the TX (shortest path over the delays):
t_sample = t_start + (i + SP)·T_bit + t_d
dominant: margin = V(t_sample) − 0.9 V
recessive: margin = 0.5 V − V(t_sample)
bit OK ⇔ margin > 0
settling = (last instant in the bit outside the valid region − bit start) / T_bit
At the end of the sequence there is a recessive "idle" bit, which also checks the return to rest.
7.13 Power
P_termination(t) = V(t)² / R
TX: I_SUP(t) = I_rec + (I_dom − I_rec)·|I_out(t)| / I_bus,60, I_bus,60 = V_open/(60 + R_dom)
P_sup = VSUP·(I_SUP + I_VCCOUT)
P_bus = V·I_out
P_diss = P_sup − 5 V·I_VCCOUT − P_bus
RX: P_diss = VSUP·(I_rec + I_VCCOUT) − 5 V·I_VCCOUT + V²/RID
Steady-state estimate: P = d·P_dom + (1 − d)·P_rec, d = % dominant
P_dom and P_rec are averages over the last 40% of each bit, i.e. with settled edges.
8. Practical CAN-FD design rules
Indicative rules, always to be checked against the transceiver datasheet, the standards (ISO 11898-2, SAE J2284, CiA 601) and the vehicle/machine maker's guidelines.
- Linear topology: one backbone with short stubs. Stars and trees are possible only at low bit rates or with very short segments.
- Exactly two 120 Ω terminations, at the electrical ends of the backbone (not necessarily on the physically farthest nodes if there are long stubs).
- Short stubs: rule of thumb 2·t_pd,stub < t_r/3. With a 5 ns/m cable and 20–40 ns edges you get about 0.3 m, the typical value quoted for classic CAN. In FD at 5–8 Mbit/s it often pays to stay below 10–30 cm.
- 120 Ω cable and traces: on the PCB short segments (a few cm) at 100–130 Ω have little effect; long ones must be designed.
- Data-phase sample point typically 70–80%. The later it is, the more time reflections have to die out.
- Capacitance: every extra pF slows the edges and lowers the local impedance. Choose low-capacitance ESD diodes for CAN-FD; capacitors to ground only if needed for EMI, and small.
- Common-mode choke: it helps with EMI, but its leakage inductance can cause ringing in FD. Check it with the blackbox cell.
- Total length: in arbitration the bit must contain the round trip on the bus plus the transceiver delays. In the data phase the own transceiver delay is compensated by the controller (TDC), but reflections remain.
- Split termination (2×60 Ω with a capacitor to ground at the midpoint): differentially it is 120 Ω; the benefit is on the common mode, not visible in this differential simulator.
- Worst case: try every end node as TX, IBIS min/max corners, cables at maximum length.
9. Reading results and troubleshooting
| Symptom | Likely cause | What to try |
|---|---|---|
| Large ringing after every edge | long stubs, unterminated ends, lots of capacitance | shorten the stubs, check the two terminations, reduce the C |
| Low dominant level (< 1.5 V) | too many terminations (load < 50 Ω), high Rout | remove extra terminations, check the DC load |
| Recessive does not return to 0 | no termination (bus "charged") | insert the terminations at the ends |
| Wrong bits on one node only | node at the end of a long stub or after a cell that filters too much | shorten the stub, move the tap, revise the cell |
| Very slow edges | high total capacitance, filter with −3 dB in band, long lossy cable | reduce the C, choose cells with a higher −3 dB |
| Γ ≈ +1 at the backbone end | missing termination | click the resistor |
| "N samples needed (limit…)" | electrically very short segments or connectors, long window | increase the max step, shorten the tail, merge segments of a few mm |
| "Zdiff far from 120 Ω" warning | undersized PCB pair | adjust W/S/layer in the stack-up |
| Clamp always conducting | trigger voltage below ~3.5 V (with Vcm 2.5 V) | use the real V_BR of the TVS (e.g. 24–27 V) |
Margin: above +0.3 V is comfortable, between 0 and +0.3 V is marginal, negative is an error. Settling: below 70% of the sample point is comfortable; close to or past the sample point is critical.
10. Model limitations
- Differential mode only, with a fixed common mode (Vcm). It does not simulate EMC emissions/immunity, CANH/CANL asymmetries, common-mode split termination, ground shift.
- Uniform impedance per segment (no variation along the cable), no crosstalk between cables.
- Closed-form formulas for the PCB (±5–10%); solder mask, copper roughness and εr dispersion are not considered.
- Connectors as equivalent line segments; lumped blackbox cells (no S-parameters/Touchstone).
- IBIS: differential equivalent of the single-ended curves; the driver's internal delay is removed; very close transitions (bits shorter than the edge) are approximated.
- Power based on datasheet supply currents (maximum values), without the capacitance charging current or the logic (VIO).
- It does not replace SPICE, measurements or compliance tests.
11. Reference values
Transceiver (default TCAN4551-Q1, TCAN455x family, TI datasheet)
| Parameter | Value |
|---|---|
| Dominant VOD (R_L 50–65 Ω) | 1.5 – 3 V |
| Receiver thresholds | dominant > 0.9 V, recessive < 0.5 V |
| RID | 60 – 100 kΩ (default 80 kΩ) |
| CI (pin to ground) | 25 pF typ. |
| CID (differential) | 14 pF typ. |
| Differential tR/F | 8 – 75 ns (55 typ., with a 100 pF load); default 40 ns |
| Recessive / dominant ISUP @60 Ω | 15 mA / 80 mA (max) |
| VSUP | 5.5 – 30 V |
| CAN-FD bit rate | up to 8 Mbit/s |
TCAN1044 IBIS model (typ, as imported): VOD @45/60/65 Ω = 1.95 / 2.19 / 2.26 V; rise/fall ≈ 26 / 45 ns; RID ≈ 160 kΩ; differential C ≈ 6.2 pF.
Typical CAN cable (e.g. LAPP UNITRONIC BUS CAN 2×2×0.34): Z0 120 Ω ±15%; NVP 0.76 (4.4 ns/m); attenuation 0.4 / 1.2 / 4.0 / 6.6 / 9.0 dB/100 m at 0.1 / 1 / 5 / 10 / 20 MHz; loop resistance ≤ 122 Ω/km.
Laminates: FR-4 εr 4.0–4.6, tan δ ≈ 0.02; 1 oz copper ≈ 35 µm.
Useful conversions
delay [ns/m] = 3.336 / NVP (NVP 0.66 → 5.05 ns/m; 0.76 → 4.39 ns/m)
dB = 20·log10(V2/V1) 1 Np = 8.686 dB
T_bit [ns] = 1000 / bitrate[Mbit/s] (5 Mbit/s → 200 ns; 8 Mbit/s → 125 ns)
12. Configuration file format (JSON)
Top-level structure (useful to generate topologies from scripts):
{
"v": 2,
"lib": {
"cables": [{ "id": "cLapp", "name": "...", "z0": 120, "nvp": 0.76, "rdc": 61, "att": [[0.1, 0.4], [1, 1.2]] }],
"boards": [{ "id": "bECU", "name": "ECU", "color": "#5eead4", "lab": 0.03,
"layers": [{ "type": "cu", "name": "L1", "t": 35, "plane": false },
{ "type": "diel", "name": "Prepreg", "t": 200, "er": 4.2, "tand": 0.02 }],
"pairs": [{ "id": "pTop", "name": "CAN top", "layer": 1, "w": 0.15, "s": 0.3, "zOver": 0 }] }],
"conns": [{ "id": "kApp", "name": "...", "kind": "conn", "mode": "lcr", "L": 20, "C": 2, "R": 10, "Z": 100, "td": 100 }],
"blks": [{ "id": "bkESD", "name": "...", "kind": "esd", "rs": 0, "ls": 0, "cp": 0,
"a": { "clg": 30, "cll": 0, "rll": 0, "vc": 27, "rd": 1, "bi": true }, "b": {} }],
"xcvrs": [{ "id": "xTCAN", "name": "TCAN4551-Q1", "rid": 80000, "ci": 25, "cid": 14,
"vopen": 3, "rdom": 20, "t1090": 40, "isupRec": 15, "isupDom": 80,
"model": "ibis", "useIbis": true, "ibis": { } }]
},
"sig": { "bitrate": 5, "pattern": "0011", "hiz": true, "vcm": 2.5, "start": 100, "settle": 600, "dtmax": 0.5, "sp": 75, "duty": 50 },
"bb": { "chain": [{ "t": "sec", "m": "cable:cLapp", "len": 8 }, { "t": "conn", "k": "kApp" }, { "t": "blk", "k": "bkESD" }],
"termL": { "on": true, "r": 120 }, "termR": { "on": true, "r": 120 } },
"mids": [{ "x": 4, "r": 120, "on": false }],
"stubs": [{ "id": "nB", "name": "Node_B", "parent": "bb", "pos": 4.06, "side": -1, "dev": true,
"xcvr": "xTCAN", "cesd": 0, "vsup": 12, "ivcc": 0, "termOn": false, "termR": 120,
"chain": [{ "t": "sec", "m": "pcb:bECU:pTop", "len": 0.03 }] }],
"tx": "tx",
"probe": { "line": "nB", "frac": 1 }
}
- Segment media:
cable:<id>orpcb:<board>:<pair>. - Lengths in metres, positions in metres from the start of the parent branch, thicknesses in µm, W/S in mm.
"pattern":0= dominant,1= recessive.- The file does not depend on the interface language: a configuration saved in Italian loads in English and vice versa (names stay as they were written).
13. FAQ
Why doesn't the plot start at bit zero? The first 100 ns ("Sequence start") are idle, to show the initial state.
Why is the simulation sometimes slow? The time step depends on the shortest segment: a 50 ps connector or a 5 mm trace force steps of ~10 ps. Merge negligible segments or increase the max step.
Can I simulate arbitration with two TXs? Not yet: there is one transmitter at a time. You can, however, choose any node as TX.
Which bit rate should I set? The CAN-FD data phase one (the most critical). For the arbitration phase set the nominal bit rate (e.g. 0.5 Mbit/s).
Why must two identical boards be created separately? Each board is a physical PCB and draws its own box. Use "Duplicate" in the library.
Is the .ibs file sent anywhere? No, it is read only in the browser. The extracted model is saved in the configuration (JSON and browser storage).
Can I use it on a phone? It works, but it is designed for desktop (dragging, Ctrl + wheel zoom).
Where does my data go? Into the browser's local storage (last configuration) and the files you save. In the published version direct download may be blocked: use "Copy" in the export windows.
Why are some names still in Italian after switching to English? Names are part of your configuration (nodes, boards, library items). An untouched preset is rebuilt in the new language; a topology you edited keeps the names it has — rename them in the Inspector or in the libraries.
14. Version history
| Version | Content |
|---|---|
| v0 (Python/Tkinter) | Original simulator: backbone, radial stubs, terminations, probe, traveling waves |
| v1 | Dark web app, interactive topology with values on the elements, stubs from stubs, animation, bit check, diagnostics |
| v2 | Chained branches (cables, PCB traces, connectors), explicit boards with stack-up editor and live cross-section, frequency-dependent losses, pin capacitances, TCAN4551-Q1, tooltips |
| v3 | Consumed/dissipated power per node and termination, topology zoom/pan, movable board labels, fine 1 mm step |
| v4 | IBIS import and non-linear transceiver simulation, blackbox cells (filters, CMC, ESD/TVS) with frequency response |
| v5 | Built-in wiki (F1), bilingual English/Italian interface (English by default) |