CANCAN Topology Lab

CAN termination: how many, where, and what goes wrong

Guide · updated on 2026-11-10

This guide is about the conventional linear High-Speed CAN bus (ISO 11898-2): one backbone with short stubs. In that topology there are two nominal 120 Ω terminations between CANH and CANL, one at each electrical end of the backbone, and no other low-value terminations on intermediate nodes:

RT=120Ω∥120Ω=60Ω

What matters is the topology of the backbone, not which node is geometrically farthest away.

The DC load

Seen in DC, the terminations and the differential input resistances of all transceivers are in parallel:

RDC=(1RT1+1RT2+∑1RID,i)−1

Transceiver inputs are not open circuits, and with many nodes they count. Example: two 120 Ω terminations and 32 transceivers with a differential input resistance of 12 kΩ each (the low end of the range allowed for receivers):

RRX=12kΩ32=375ΩRDC=60Ω∥375Ω≈51.7Ω

So the effective load can be below 60 Ω even with exactly the right terminations. The 50–65 Ω range in ISO 11898-2 is the effective resistive load under which the transmitter must guarantee its dominant output, at least 1.5 V differential. It is a load condition for the driver specification rather than a generic target for the network, but it is a good reference for checking a design.

A multimeter reading of about 60 Ω between CANH and CANL tells you the terminations are there. It does not prove that the line is matched at high frequency: a network with the right DC resistance can still have signal-integrity problems from stubs and discontinuities.

Three cases

Two correct end terminations. At each end of the backbone ZL=Z0=120Ω, so Γ=0 and the incoming edge is absorbed. This minimises reflections at the backbone ends; reflections can still come from long stubs, branches, connectors, cabling and transceiver input capacitance.

A single termination. The unterminated end behaves approximately as an open circuit:

ZL→∞⇒ΓL=ZL−Z0ZL+Z0→+1

The edge is reflected with the same polarity, causing strong reflections that can produce overshoot, undershoot and ringing. How severe it is depends on line length, driver impedance, edge times and the other loads; settling takes longer and a receiver may sample a wrong value. The recessive state itself is still defined by

Vdiff=VCANH−VCANL

which settles back towards 0 V, with both wires biased around 2.5 V: a single termination delays and disturbs that return, it does not prevent it.

Too many terminations. Three 120 Ω resistors already give

120∥120∥120=40Ω

Below 50 Ω the driver is increasingly overloaded and its dominant differential voltage may decrease, possibly below the 1.5 V minimum guaranteed under the standard 50–65 Ω load. How much it drops depends on the transceiver.

Worth remembering

  • Terminations stay at the ends of the backbone. A long stub is not fixed by putting a termination at its far end: it remains a branch that adds an impedance discontinuity.
  • In a conventional linear bus, intermediate terminations should generally be avoided: they add a discontinuity, reflections and extra load on the driver. Special topologies (for example some star networks, or high-value terminations on branch nodes) may use other strategies, but they must be designed and validated for that specific network.
  • Split termination puts two 60 Ω resistors in series at each end, with a capacitor from the midpoint to ground:
RT,diff=60Ω+60Ω=120Ω

Differentially it is still 120 Ω. It filters common-mode noise and improves the symmetry of CANH and CANL, which helps reduce emissions. Those benefits are not visible in a purely differential simulator like this one.

In the simulator, try the “No terminations”, “Single termination” and “Too many terminations” presets and compare the waveform and the diagnostics.

A pre-layout and what-if tool: it does not replace SPICE, measurements or compliance testing. See the technical disclaimer.
Try it on your own bus.

Draw the topology, pick the bit rate and check the voltage margin at every receiver's sample point. It runs in your browser: your topologies and files are never uploaded.

Open the simulator